This invention relates to a semiconductor memory device.
To improve the yield of products, the application of redundancy techniques to semiconductor memory devices (hereinafter referred to as the "memory") has been examined. Fail bits for which read and write of data are not possible are unavoidably formed in memory devices due to the variance of production conditions or to defects in masks used for the production. To cope with this problem, spare bits are disposed in advance in the memory so that they are selected in place of the fail bits. Thus, the memory can be regarded as if it were free from the fail bits.
When applying the redundancy-relieving techniques to a memory, an arrangement has been considered in which spare columns (constituted by spare data lines and spare bits connected to the former) are provided so that the spare columns are selected in place of the defective data lines containing the fail bits. In other words, additional circuits such as the spare columns, an address comparison circuit and a memory circuit for storing the address signals of the defective columns are disposed in the memory. When the address signals are applied to the memory, they are compared with the address signals of defective columns stored in the memory circuit by the address comparison circuit. When the address signals applied to the memory coincide with the address signals of the defective columns stored in the memory circuit, a coincidence signal is generated from the address comparison circuit. This coincidence signal brings the column containing the fail bits (defective data lines) into the non-selection state and instead, the spare columns are selected.
In the course of developing the invention, the inventors designed a memory of a byte (.times.8 bits) construction, that is, a memory in which write and read of data is effected in the 8-bit unit. Such a memory was constructed so that eight memory arrays (mats) were disposed and one bit each was selected from each memory array so that 8-bit data could be read or written. In such a memory, column decoders and column switches were densely formed in order to select one bit from each memory array. From the inventors' experiments with this memory it was determined that if the redundancy techniques which change over the defective data lines to the spare data lines are applied to such a memory, it becomes difficult to change over the defective data lines to the spare data lines. The changeover operation for changing the defective data lines to the spare data lines for each memory array becomes complicated, too.
In the memory of the type described above, delicate fabrication techniques using a laser beam may be employed as a method of changing the defective data lines to the spare data lines. In other words, the wirings themselves are changed over from the defective data lines to the spare data lines by the laser beam.
To change over the wirings by such a laser beam, expensive equipment becomes necessary and hence, the cost of production of the semiconductor memory device becomes higher while the test efficiency drops.
Accordingly, the inventors of the present invention allot the multi-bit address to a plurality of data lines adjacent one another inside the same memory array (mat) in order to secure a space in which a column address decoder is formed, and change over the plurality of data lines as a lot (i.e. a unit) to a plurality of spare data lines when a defect exists in the memory array data lines. Also, the present invention provides an arrangement having at least one spare memory array used in conjunction with at least two memory arrays with a redundancy circuit and change-over circuit for recognizing when the data line address request for either of the memory arrays is for a location having a fail bit and for selecting a data line from the spare memory when this occurs. To this end, either the first or second memory arrays can be selected under normal operation and the spare memory array can be selected when a defective location is requested, and this can be accomplished without the need for a laser beam rewiring structure.
In addition to the above, in fabricating a semiconductor memory device having a large memory capacity such as 256K bits (8.times.32K bits), for example, the memory mat is preferably divided into a plurality of memory mats in order to reduce the length of word lines and data lines and to improve its high speed operation. The present invention provides an arrangement to improve the utilization ratio of the spare data lines, that is, the relief ratio of the fail bits, by using the spare data lines in the one mat not only as spare data lines for said one mat but also as spare data lines in the other mat, that is, by using the spare data lines in the one mat selectively as spare data lines for the one mat or as spare data lines in the other mat, when the memory mat is divided into a plurality of mats.